1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a static type semiconductor RAM (Random Access Memory) device having a large memory capacity and a high operating speed.
2. Description of the Prior Art
In general, the current consumption of memory cells and bit lines of a static type RAM device becomes large according to an increase in the memory capacity, i.e., according to an increase in the number of the memory cells. Therefore, especially in a RAM device having a large memory capacity, the gm of each of the load transistors connected to the bit lines is caused to be small in order to decrease the current consumption of the bit lines.
As illustrated in FIG. 1, a conventional static type RAM device comprises a plurality of memory cells MC.sub.0,0, MC.sub.1,0, . . . ; word lines W.sub.0, W.sub.1, . . . ; pairs of bit lines B.sub.0 and B.sub.0, . . . ; word decoders WD.sub.0, WD.sub.1, . . . ; and load MIS transistors Q.sub.1, Q.sub.2, . . . for each of the bit lines B.sub.0 and B.sub.0. Each of the memory cells MC.sub.0,0, MC.sub.1,0, . . . has the same circuit structure and comprises load resistors R.sub.1 and R.sub.2 and MIS transistors Q.sub.3 through Q.sub.6. The drain electrodes and the gate electrodes of the transistors Q.sub.5 and Q.sub.6 are cross-coupled so as to form a flip-flop type memory cell circuit.
In the memory device of FIG. 1, when, for example, the word line W.sub.0 is selected by address signals ADD and the output potential of the word decoder WD.sub.0, i.e., the word line W.sub.0 becomes the potential level for a selected condition, for example high, the transistors Q.sub.3 and Q.sub.4 are both turned on. In this condition, if the transistors Q.sub.6 of the memory cell MC.sub.0,0 is in an on state, a current flows from a voltage source V.sub.DD through the transistors Q.sub.2, Q.sub.4 and Q.sub.6 to another voltage source V.sub.SS, so that the potential of the bit line B.sub.0 becomes low. Since the transistor Q.sub.5 of the same memory cell MC.sub.0,0 is in a turned off condition, the potential level of the bit line B.sub.0 is high. The potential difference between the bit lines B.sub.0 and B.sub.0 is detected by a sense amplifier (not shown in the drawing) and information from the selected memory cell MC.sub.0,0 is provided as an output.
In the above-mentioned RAM device, if the memory cell MC.sub.1,0 is selected next after the memory cell MC.sub.0,0 and if the memory cell MC.sub.1,0 stores a different data from that of the memory cell MC.sub.0,0, i.e., a transistor Q'.sub.5 is in a turned on condition and a transistor Q'.sub.6 is in a turned off condition, it is necessary to electrically charge the bit line B.sub.0 to a high potential level quickly. However, since, as aforementioned, the gm of the load transistors Q.sub.1 and Q.sub.2 is caused to be small in order to decrease the current consumption of the bit lines of a memory device having a large memory capacity, it is impossible to quickly charge the bit line B.sub.0 from low to high. Therefore, the access time of such a conventional memory device cannot be short. If the read-out of information from the memory cell MC.sub.1,0 is effected just after the write-in of information to the memory cell MC.sub.0,0 and if the memory cell MC.sub.1,0 stores data different from that written into the memory cell MC.sub.0,0, it is necessary to electrically charge the bit line, for example, B.sub.0, from a very low potential (e.g. 0 V) to a high potential (e.g. 3 V), so that the access time of the RAM device becomes still longer than that in the above-mentioned case.